Advanced Features
Manual Clock Switchover
Stratix II and Stratix II GX enhanced and fast PLLs support manual
switchover, where the clkswitchsignal controls whether inclk0or
inclk1is the input clock to the PLL. If clkswitchis low, then inclk0
is selected; if clkswitchis high, then inclk1is selected. Figure 1–23
shows the block diagram of the manual switchover circuit in fast PLLs.
The block diagram of the manual switchover circuit in enhanced PLLs is
shown in Figure 1–23.
Figure 1–23. Manual Clock Switchover Circuitry in Fast PLLs
clkswitch
inclk0
n Counter
PFD
inclk1
muxout
refclk
fbclk
Figure 1–24 shows an example of a waveform illustrating the switchover
feature when controlled by clkswitch. In this case, both clock sources
are functional and inclk0is selected as the primary clock. clkswitch
goes high, which starts the switch-over sequence. On the falling edge of
inclk0, the counter’s reference clock, muxout, is gated off to prevent
any clock glitching. On the rising edge of inclk1, the reference clock
multiplex switches from inclk0to inclk1as the PLL reference. When
the clkswitchsignal goes low, the process repeats, causing the circuit to
switch back from inclk1to inclk0.
1–40
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
ALTERA [ ALTERA CORPORATION ]
