PLLs in Stratix II and Stratix II GX Devices
Figure 1–24. Manual Switchover Note (1)
inclk0
inclk1
muxout
clkswitch
Note to Figure 1–24:
(1) Both inclk0and inclk1must be running when the clkswitchsignal goes high to initiate a manual clock
switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
Software Support
Table 1–15 summarizes the signals used for clock switchover.
Table 1–15. altpll Megafunction Clock Switchover Signals
(Part 1 of 2)
Port
Description
Source
Destination
inclk0
inclk1
Reference clk0to the PLL.
Reference clk1to the PLL.
I/O pin
I/O pin
Clock switchover circuit
Clock switchover circuit
Logic array
clkbad0(1)
clkbad1(1)
clkswitch
Signal indicating that inclk0is no longer Clock switchover
toggling. circuit
Signal indicating that inclk1is no longer Clock switchover
toggling.
Logic array
circuit
Switchover signal used to initiate clock
switchover asynchronously. When used in
manual switchover, clkswitch is used as a
select signal between inclk0 and inclk1
clswitch = 0 inclk0is selected
and vice versa.
Logic array or I/O pin Clock switchover circuit
clkloss(1)
Signal indicating that the switchover
circuit detected a switch condition.
Clock switchover
circuit
Logic array
locked
Signal indicating that the PLL has lost
lock.
PLL
Clock switchover circuit
Altera Corporation
July 2009
1–41
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
