PLLs in Stratix II and Stratix II GX Devices
Figure 1–28. High-Bandwidth PLL Lock Time
160
155
150
145
Lock Time = 4 μs
Frequency (MHz)
140
135
130
125
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (μs)
A high-bandwidth PLL can benefit a system that has two cascaded PLLs.
If the first PLL uses spread spectrum (as user-induced jitter), the second
PLL can track the jitter that is feeding it by using a high-bandwidth
setting. A low-bandwidth PLL can, in this case, lose lock due to the
spread-spectrum-induced jitter on the input clock.
A low-bandwidth PLL benefits a system using clock switchover. When
the clock switchover happens, the PLL input temporarily stops. A
low-bandwidth PLL would react more slowly to changes to its input
clock and take longer to drift to a lower frequency (caused by the input
stopping) than a high-bandwidth PLL. Figures 1–29 and 1–30
demonstrate this property. The two plots show the effects of clock
switchover with a low- or high-bandwidth PLL. When the clock
switchover happens, the output of the low-bandwidth PLL (see
Figure 1–29) drifts to a lower frequency more slowly than the
high-bandwidth PLL output (see Figure 1–30).
Altera Corporation
July 2009
1–47
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
