Advanced Features
Figure 1–18. Automatic Switchover Upon Clock Loss Detection
inclk0
inclk1
(1)
(2)
muxout
refclk
fbclk
clk0bad
(3)
(4)
clk1bad
lock
activeclock
clkloss
PLL Clock
Output
Notes to Figure 1–18:
(1) The number of clock edges before allowing switchover is determined by the counter setting.
(2) Switchover is enabled on the falling edge of INCLK1.
(3) The rising edge of FBCLKcauses the VCO frequency to decrease.
(4) The rising edge of REFCLKstarts the PLL lock process again, and the VCO frequency increases.
1–36
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
