Hardware Features
Table 1–13. Stratix II and Stratix II GX PLL Hardware Features (Part 2 of 2)
Availability
Hardware Features
Enhanced PLL
Fast PLL
Phase shift
Down to 125-ps increments (3)
Down to 125-ps increments (3)
Programmable duty cycle
Yes
Yes
Notes to Table 1–13:
(1) Post-scale counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using
a non-50% duty cycle, the post-scale counters range from 1 through 256.
(2) Post-scale counters range from 1 through 32 if the output clock uses a 50% duty cycle. For any output clocks using
a non-50% duty cycle, the post-scale counters range from 1 through 16.
(3) The smallest phase shift is determined by the VCO period divided by 8. For degree increments, the Stratix II device
can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on
the frequency and divide parameters.
Clock Multiplication and Division
Each Stratix II PLL provides clock synthesis for PLL output ports using
m/(n × post-scale counter) scaling factors. The input clock is divided by a
pre-scale factor, n, and is then multiplied by the m feedback factor. The
control loop drives the VCO to match fIN (m/n). Each output port has a
unique post-scale counter that divides down the high-frequency VCO.
For multiple PLL outputs with different frequencies, the VCO is set to the
least common multiple of the output frequencies that meets its frequency
specifications. For example, if output frequencies required from one PLL
are 33 and 66 MHz, then the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz within the VCO range).
Then, the post-scale counters scale down the VCO frequency for each
output port.
There is one pre-scale counter, n, and one multiply counter, m, per PLL,
with a range of 1 to 512 for both m and n in enhanced PLLs. For fast PLLs,
m ranges from 1 to 32 while n ranges from 1 to 4. There are six generic
post-scale counters in enhanced PLLs that can feed regional clocks, global
clocks, or external clock outputs, all ranging from 1 to 512 with a 50%
duty cycle setting for each PLL. The post-scale counters range from 1 to
256 with any non-50% duty cycle setting. In fast PLLs, there are four
post-scale counters (C0, C1, C2, C3) for the regional and global clock
output ports. All post-scale counters range from 1 to 32 with a 50% duty
cycle setting. For non-50% duty cycle clock outputs, the post-scale
counters range from 1 to 16. If the design uses a high-speed I/O interface,
you can connect the dedicated dffioclkclock output port to allow the
high-speed VCO frequency to drive the serializer/deserializer (SERDES).
1–26
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
