PLLs in Stratix II and Stratix II GX Devices
Figure 1–13. Phase Relationship Between PLL Clocks in External Feedback
Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at
the Register
Clock Port (1)
External PLL
Clock Outputs (1)
f
Clock Input
BIN
Note to Figure 1–13:
(1) The PLL clock outputs can lead or lag the fBIN clock input.
Stratix II and Stratix II GX PLLs support a number of features for
general-purpose clock management. This section discusses clock
multiplication and division implementation, phase-shifting
implementations and programmable duty cycles. Table 1–13 shows
which feature is available in which type of Stratix II or Stratix II GX PLL.
Hardware
Features
Table 1–13. Stratix II and Stratix II GX PLL Hardware Features (Part 1 of 2)
Availability
Hardware Features
Enhanced PLL
Fast PLL
Clock multiplication and division
m counter value
m (n × post-scale counter)
Ranges from 1 through 512
Ranges from 1 through 512
Ranges from 1 through 512 (1)
m (n × post-scale counter)
Ranges from 1 through 32
Ranges from 1 through 4
Ranges from 1 through 32 (2)
n counter value
Post-scale counter values
Altera Corporation
July 2009
1–25
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
