PLLs in Stratix II and Stratix II GX Devices
The Quartus II software automatically chooses the appropriate scaling
factors according to the input frequency, multiplication, and division
values entered into the altpllmegafunction.
Phase-Shift Implementation
Phase shift is used to implement a robust solution for clock delays in
Stratix II and Stratix II GX devices. Phase shift is implemented by using a
combination of the VCO phase output and the counter starting time. The
VCO phase output and counter starting time is the most accurate method
of inserting delays, since it is purely based on counter settings, which are
independent of process, voltage, and temperature.
1
Stratix II and Stratix II GX PLLs do not support programmable
delay elements because these delay elements require
considerable area on the die and are sensitive to process,
voltage, and temperature.
You can phase shift the output clocks from the Stratix II or Stratix II GX
enhanced PLL in either:
■
■
Fine resolution using VCO phase taps
Coarse resolution using counter starting time
The VCO phase tap and counter starting time is implemented by allowing
any of the output counters (C[5..0]or m) to use any of the eight phases
of the VCO as the reference clock. This allows you to adjust the delay time
with a fine resolution. The minimum delay time that you can insert using
this method is defined by:
1
8
1
N
Φfine
=
TVCO
=
=
8fVCO 8MfREF
where fREF is input reference clock frequency.
For example, if fREF is 100 MHz, n is 1, and m is 8, then fVCO is 800 MHz
and fINE equals 156.25 ps. This phase shift is defined by the PLL
operating frequency, which is governed by the reference clock frequency
and the counter settings.
You can also delay the start of the counters for a predetermined number
of counter clocks. You can express phase shift as:
(C − 1)N
MfREF
C − 1
fVco
Φcoarse
=
=
Altera Corporation
July 2009
1–27
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
