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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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PLLs in Stratix II and Stratix II GX Devices  
Programmable Duty Cycle  
The programmable duty cycle allows enhanced and fast PLLs to generate  
clock outputs with a variable duty cycle. This feature is supported on  
each enhanced and fast PLL post-scale counter C[]. The duty cycle  
setting is achieved by a low and high time count setting for the post-scale  
counters. The Quartus II software uses the frequency input and the  
required multiply or divide rate to determine the duty cycle choices. The  
post-scale counter value determines the precision of the duty cycle. The  
precision is defined by 50% divided by the post-scale counter value. The  
closest value to 100% is not achievable for a given counter value. For  
example, if the C0counter is ten, then steps of 5% are possible for duty  
cycle choices between 5 to 90%.  
If the device uses external feedback, you must set the duty cycle for the  
counter driving the fbinpin to 50%. Combining the programmable duty  
cycle with programmable phase shift allows the generation of precise  
non-overlapping clocks.  
Advanced Clear and Enable Control  
There are several control signals for clearing and enabling PLLs and their  
outputs. You can use these signals to control PLL resynchronization and  
gate PLL output clocks for low-power applications.  
Enhanced Lock Detect Circuit  
The lock output indicates that the PLL has locked onto the reference clock.  
Without any additional circuitry, the lock signal may toggle as the PLL  
begins tracking the reference clock. You may need to gate the lock signal  
for use as a system control. Either a gated lock signal or an ungated lock  
signal from the locked port can drive the logic array or an output pin. The  
Stratix II and Stratix II GX enhanced and fast PLLs include a  
programmable counter that holds the lock signal low for a user-selected  
number of input clock transitions. This allows the PLL to lock before  
enabling the lock signal. You can use the Quartus II software to set the  
20-bit counter value.  
Altera Corporation  
July 2009  
1–29  
Stratix II Device Handbook, Volume 2  
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