Timing Model
I/O Delays
See Tables 5–72 through 5–76 for I/O delays.
Table 5–72. I/O Delay Parameters
Symbol
Parameter
tDIP
Delay from I/O datain to output pad
tOP
Delay from I/O output register to output pad
Delay from input pad to I/O dataout to core
Delay from input pad to I/O input register
tPCOUT
tPI
Table 5–73. Stratix II I/O Input Delay for Column Pins (Part 1 of 3)
Minimum Timing
-3Speed -3Speed
-4Speed -5Speed
I/O Standard
Parameter
Grade
Grade
(3)
Unit
Grade
Grade
Industrial Commercial
(2)
LVTTL
tPI
674
408
684
418
747
481
749
483
674
408
507
241
507
241
543
277
543
277
560
294
707
428
717
438
783
504
786
507
707
428
530
251
530
251
569
290
569
290
587
308
1223
787
1282
825
1405
904
1637
1054
1619
1036
1829
1246
1922
1339
1637
1054
1094
511
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
2.5 V
1210
774
1269
812
1390
889
1.8 V
1366
930
1433
976
1570
1069
1650
1149
1405
904
1.5 V
1436
1000
1223
787
1506
1049
1282
825
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
818
857
939
382
400
438
818
857
939
1094
511
tPCOUT
382
400
438
SSTL-18 Class I tPI
tPCOUT
SSTL-18 Class II tPI
tPCOUT
tPI
tPCOUT
898
941
1031
530
1201
618
462
484
898
941
1031
530
1201
618
462
484
1.5-V HSTL
Class I
993
1041
584
1141
640
1329
746
557
5–54
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
