Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 2 of 8)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(4)
LVCMOS
4 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
1041
1061
952
972
926
946
933
953
921
941
909
929
1004
1024
955
975
934
954
918
938
1091
1113
999
2036
2102
1786
1852
1720
1786
1693
1759
1677
1743
1659
1725
2063
2129
1841
1907
1742
1808
1679
1745
2136
2206
1874
1944
1805
1875
1776
1846
1759
1829
1741
1811
2165
2235
1932
2002
1828
1898
1762
1832
2340
2416
2053
2129
1977
2053
1946
2022
1927
2003
1906
1982
2371
2447
2116
2192
2002
2078
1929
2005
2448
2538
2153
2243
2075
2165
2043
2133
2025
2115
2003
2093
2480
2570
2218
2308
2101
2191
2027
2117
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
1021
971
12 mA
16 mA
20 mA
993
978
1000
965
987
24 mA
(1)
954
976
2.5 V
4 mA
8 mA
12 mA
1053
1075
1001
1023
980
1002
962
16 mA
(1)
984
5–58
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
