Timing Model
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, intra-clock network skew
adder is not specified. Table 5–68 specifies the clock skew between any
two clock networks driving registers in the IOE.
Table 5–68. Clock Network Specifications
Name
Description
Min
Typ
Max
Unit
Clock skew adder
EP2S15, EP2S30,
EP2S60 (1)
Inter-clock network, same side
Inter-clock network, entire chip
50
ps
ps
100
Clock skew adder
EP2S90 (1)
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
55
110
63
ps
ps
ps
ps
ps
ps
Clock skew adder
EP2S130 (1)
125
75
Clock skew adder
EP2S180 (1)
150
Note to Table 5–68:
(1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
5–50
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
