Timing Model
Table 5–42. M-RAM Block Internal Timing Microparameters (Part 1 of 2)
Note (1)
-4 Speed
-3 Speed
-3 Speed
-5 Speed
Grade
Grade (2)
Grade (3)
Grade
Symbol
Parameter
Unit
Min
(4)
Min
(4)
Min
Min
(4)
Max
Max
Max
Max
(5)
tMEGARC
Synchronous read cycle 1,866 2,774 1,866 2,911 1,777 3,189 1,777 3,716 ps
time
1,866
1,866
tMEGAWERESU Write or read enable
setup time before clock
144
39
151
40
165
165
192
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tMEGAWEREH
tMEGABESU
tMEGABEH
Write or read enable
hold time after clock
44
44
52
67
Byte enable setup time
before clock
50
52
57
57
Byte enable hold time
after clock
39
40
44
44
52
tMEGADATAASU A port data setup time
before clock
50
52
57
57
67
tMEGADATAAH
A port data hold time
after clock
243
589
255
618
253
52
279
279
325
789
322
67
tMEGAADDRASU A port address setup
time before clock
677
677
tMEGAADDRAH A port address hold time 241
after clock
277
277
tMEGADATABSU B port setup time before
clock
50
57
57
tMEGADATABH
B port hold time after
clock
243
589
255
618
253
480
279
279
325
789
322
480
tMEGAADDRBSU B port address setup
time before clock
677
677
tMEGAADDRBH B port address hold time 241
after clock
277
277
tMEGADATACO1 Clock-to-output delay
when using output
480
715
749
457
480
821
957
registers
tMEGADATACO2 Clock-to-output delay
without output registers
1,950 2,899 1,950 3,042 1,857 3,332 1,950 3,884 ps
1,950
tMEGACLKL
Minimum clock low time 1,250
1,312
1,437
1,437
1,675
ps
5–40
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
