Timing Model
Table 5–40. M512 Block Internal Timing Microparameters (Part 2 of 2)
Note (1)
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
(4)
Min
(4)
Min
(5)
Min
(4)
Max
Max
Max
Max
tM512DATACO1 Clock-to-output delay
when using output
298
478
298
501
284
298
548
298
640
ps
registers
tM512DATACO2 Clock-to-output delay
without output registers
2,102 2,345 2,102 2,461 2,003 2,695 2,102 3,141 ps
2,102
tM512CLKL
tM512CLKH
tM512CLR
Minimum clock low time 1,315
1,380
1,380
151
1,512
1,512
1,762
1,762
192
ps
ps
ps
Minimum clock high time 1,315
1,512
1,512
Minimum clear pulse
width
144
165
165
Notes to Table 5–40:
(1) FMAX of M512 block obtained using the Quartus II software does not necessarily equal to 1/TM512RC.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(5) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Table 5–41. M4K Block Internal Timing Microparameters (Part 1 of 2) Note (1)
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
(4)
Min
(4)
Min
(5)
Min
(4)
Max
Max
Max
Max
tM4KRC
Synchronous read cycle 1,462 2,240 1,462 2,351 1,393 2,575 1,462 3,000 ps
time
1,462
tM4KWERESU
tM4KWEREH
tM4KBESU
tM4KBEH
Write or read enable
setup time before clock
22
203
22
23
213
23
25
25
29
272
29
ps
ps
ps
ps
Write or read enable
hold time after clock
233
233
Byte enable setup time
before clock
25
25
Byte enable hold time
after clock
203
213
233
233
272
5–38
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
