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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC & Switching Characteristics  
Table 5–39. DSP Block Internal Timing Microparameters (Part 2 of 2)  
-3 Speed  
Grade (1)  
-3 Speed  
Grade (2)  
-4 Speed  
Grade  
-5 Speed  
Grade  
Symbol  
Parameter  
Unit  
Min  
Max  
(3)  
Min  
Max  
(3)  
Min  
(4)  
Min  
(3)  
Max  
Max  
tCLKL  
tCLKH  
Minimum clock low  
time  
1,190  
1,249  
1,368  
1,368  
1,594  
ps  
ps  
Minimum clock high  
time  
1,190  
1,249  
1,368  
1,368  
1,594  
Notes to Table 5–39:  
(1) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.  
(2) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.  
(3) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade  
devices offer the industrial temperature grade.  
(4) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second  
number is the minimum timing parameter for commercial devices.  
Table 5–40. M512 Block Internal Timing Microparameters (Part 1 of 2)  
Note (1)  
-3 Speed  
Grade (2)  
-3 Speed  
Grade (3)  
-4 Speed  
Grade  
-5 Speed  
Grade  
Symbol  
Parameter  
Unit  
Min  
(4)  
Min  
(4)  
Min  
(5)  
Min  
(4)  
Max  
Max  
Max  
Max  
tM512RC  
Synchronous read cycle 2,089 2,318 2,089 2.433 1,989 2,664 2,089 3,104 ps  
time  
2,089  
tM512WERESU  
tM512WEREH  
tM512DATASU  
tM512DATAH  
Write or read enable  
setup time before clock  
22  
203  
22  
23  
213  
23  
25  
25  
29  
272  
29  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
Write or read enable  
hold time after clock  
233  
233  
Data setup time before  
clock  
25  
25  
Data hold time after  
clock  
203  
22  
213  
23  
233  
233  
272  
29  
tM512WADDRSU Write address setup  
time before clock  
25  
25  
tM512WADDRH Write address hold time  
after clock  
203  
22  
213  
23  
233  
233  
272  
29  
tM512RADDRSU Read address setup  
time before clock  
25  
25  
tM512RADDRH  
Read address hold time  
after clock  
203  
213  
233  
233  
272  
Altera Corporation  
April 2011  
5–37  
Stratix II Device Handbook, Volume 1  
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