a8237 Programmable DMA Controller Data Sheet
Functional
Description
Figure 2
shows a block diagram of the
a8237
MegaCore function.
Figure 2. a8237 Block Diagram
hlda
ncs
neopin
niorin
niowin
ready
reset
ain[3..0]
dbin[7..0]
Control
Logic
(State Machine
and Decoder)
Internal
Control
Signals
hrq, aen, adstb
niorout, niowout
nmemr, nmemw
dben, dmaenable, neopout
DMA Address Registers
Channel 0
Base
Channel 1
Base
Mode
Registers
Channel 0
Channel 1
Channel 2
Channel 3
Command
Register
Temporary
Register
Channel 2
Base
Channel 3
Base
Channel 0
Current
Channel 1
Current
Channel 2
Current
Channel 3
Current
aout[7..0]
Temporary
Register
aout[15..8]
to dbout[7..0]
DMA Word Count Registers
Channel 0
Base
Channel 1
Base
Channel 2
Base
Channel 3
Base
Channel 0
Current
Channel 1
Current
Channel 2
Current
Channel 3
Current
Temporary
Register
to
Control
Logic
Status
Register
aout[15..8]
dbout[7..0]
Data
Output
Multiplexer
Request
Register
Mask
Register
Request
Priority
Encoder
dack[3..0]
Other
Registers
dreq[3..0]
clk
Programming
Several registers in the
a8237
must be programmed before DMA cycles
can be executed. However, to avoid unpredictable behavior, disable the
DMA cycles during programming by setting bit 2 of the command
register.
8
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
