a8237 Programmable DMA Controller Data Sheet
Table 1
describes the input and output ports of the
a8237
MegaCore
function.
Table 1. a8237 Ports (Part 1 of 2)
Name
clk
hlda
ncs
neopin
niorin
niowin
ready
Type
Input
Input
Input
Input
Input
Input
Input
Polarity
–
High
Low
Low
Low
Low
High
Description
Clock. Used to generate and synchronize
a8237
operations.
Hold acknowledge. This signal from the microprocessor indicates the
release of the system bus to the
a8237.
Chip select. When
ncs
is active, the
a8237
is selected, and read and
write transactions to internal registers are enabled.
End of process. Permits external termination of the current DMA service.
I/O read control. When
niorin
is low and the
a8237
is selected, read
transactions from internal registers are enabled.
I/O write control. When
niowin
is low and the
a8237
is selected, data is
asynchronously written into the
a8237.
Ready. Extends the read and write pulses associated with slow memory
or peripherals. When
ready
is low, wait states are inserted until
ready
returns high.
Reset. Clears the command, status, request, and temporary registers.
Also clears the byte pointer, mode register counter, and the controller
state machine. Sets the mask register so requests are ignored after
initialization.
Register address bus. Selects one of the internal
a8237
registers. See
Table 2 on page 9.
Data bus input. The microprocessor writes data to internal registers via
the
dbin[7..0]
bus.
DMA request bus. Programmable polarity. Asynchronous signals from
peripherals requesting DMA service.
Address strobe. Latches the MSB of the DMA address from
dbout[7..0]
into an external address latch.
Address enable. Enables an external address latch containing the most
significant address byte of a DMA transfer.
Data bus enable. Active when data registers are read. Also active during
DMA transfers, allowing the most significant bit (MSB) of the address to
latch the output of temporary register data during memory-to-memory
writes.
DMA enable. Asserted during an active DMA cycle. Can create
bidirectional signals from the
niorin, niorout, niowin,
and
niowout
signals, and the lower four bits of the address bus.
Hold request. Requests control of the system bus.
End of process. Indicates normal termination of a DMA transfer.
I/O read output. Read strobe to I/O devices as DMA writes to memory.
reset
Input
High
ain[3..0]
dbin[7..0]
dreq[3..0]
adstb
aen
dben
Input
Input
Input
Output
Output
Output
–
–
–
High
High
High
dmaenable
Output
High
hrq
neopout
niorout
Output
Output
Output
High
Low
Low
6
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