a8237 Programmable DMA Controller Data Sheet
Table 3. Command Register Format
Bit
0
1
Description
0 = Memory-to-memory disable
1 = Memory-to-memory enable
0 = Channel 0 address hold disable
1 = Channel 0 address hold enable
X if bit 0 = 0,
Note (1)
0 = Controller enable
1 = Controller disable
0 = Normal timing
1 = Compressed timing
X if bit 0 = 1,
Note (1)
0 = Fixed priority
1 = Rotating priority
0 = Late write
1 = Extended write
X if compressed timing,
Note (1)
0 =
dreq
active high
1 =
dreq
active low
0 =
dack
active low
1 =
dack
active high
2
3
4
5
6
7
Note:
(1)
The X indicates “don’t care.”
Mode Register
The 6-bit mode registers contain the configuration for each of the four
DMA channels. When writing from
dbin[7..0],
the first two bits of the
mode register format selects the DMA channel mode register. Before
reading each of the mode registers, the clear mode register counter
command must be executed. The next read from the mode register
address returns the value from the channel 0 mode register. Subsequent
mode register reads step through the other mode registers in order. See
Table 4.
12
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