a8237 Programmable DMA Controller Data Sheet
Table 4. Mode Register Format
Bit
1..0
Description
00 = Channel 0 select
01 = Channel 1 select
10 = Channel 2 select
11 = Channel 3 select
11 during Read
00 = Verify transfer
01 = Write transfer
10 = Read transfer
11 = Illegal
0 = Auto-initialization disable
1 = Auto-initialization enable
0 = Address increment
1 = Address decrement
00 = Demand mode select
01 = Single mode select
10 = Block mode select
11 = Unused (Cascade mode is not supported.)
3..2
4
5
7..6
Request Register
The 4-bit request register allows software DMA requests. Hardware
requests (from
dreq
inputs) are masked by the mask register values;
software requests generated from the request register are unmaskable.
The request register request bits can only be programmed by the single
request bit command. The
reset
input or a master clear command clears
the request register. See
Table 5.
Table 5. Request Register Format
Bit
0
1
2
3
7..4
Description
1 = Channel 0 request
1 = Channel 1 request
1 = Channel 2 request
1 = Channel 3 request
1111
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