Getting Started
You can click Back to display the previous page or click Parameters
Setting, Simulation Library, or Summary Page, if you want to change
any of the MegaWizard options.
To generate the files, follow these steps:
1. Turn on the files you want to generate (see Figure 2–6).
2. To generate the specified files and close the MegaWizard Plug-in
Manager, click Finish.
1
The generation phase may take several minutes to
complete.
When the file generation is complete, you can go to the project
directory and view a list of generated files in the file <variation
name>.html (the files that are listed in the following table).
Table 2–1 describes the generated files and other files that may be in
your project directory. The names and types of files specified in the
summary vary based on whether you created your design with
VHDL or Verilog HDL
Table 2–1. Generated Files Note (1) (Part 1 of 2)
Filename (2)
Description
<variation name>.bsf
Quartus II symbol file for the MegaCore function variation. You can
use this file in the Quartus II block diagram editor.
VHDL component declaration file
The MegaCore function report file.
<variation name>.cmp
<variation name>.html
<variation name>.v
A MegaCore function variation file, which defines a Verilog HDL
top-level description of the custom MegaCore function. Instantiate
the entity defined by this file inside of your design. Include this file
when compiling your design in the Quartus II software.
Verilog HDL IP functional simulation model.
<variation name>.vo
Verilog HDL black-box file for the MegaCore function variation.
Use this file when using a third-party EDA tool to synthesize your
design.
<variation namez>_bb.v
Tool command language (tcl) script used to set constraints.
<variation name>_constraints.tcl
<variation name>_enc8b10b.ocp
An OpenCore Plus file, needed for time-limited or tethered
hardware evaluation.
Verilog HDL RTL for this MegaCore function variation.
<variation name>_enc8b10b.v
A Tcl script to automate the process of running the provided demo
testbench with the IP functional simulation model.
<variation name>_run_modelsim.tcl
Altera Corporation
October 2007
MegaCore Version 7.2
2–9
8B10B Encoder/Decoder MegaCore Function User Guide
ALTERA [ ALTERA CORPORATION ]
