Getting Started
3. Select the mode of operation, either Encoder or Decoder.
4. If you selected Encoder, turn on the Register inputs/outputs check
box for a three cycle latency, or turn off the Register inputs/outputs
check box for a single cycle latency.
1
The Decoder always has registered inputs and outputs.
5. Click Next (or the Simulation Model tab) to display the simulation
setup page (see Figure 2–5).
Figure 2–5. Simulation Model
Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or
Verilog HDL model file produced by the Quartus II software. The model
allows for fast functional simulation of IP using industry-standard VHDL
and Verilog HDL simulators.
Altera Corporation
October 2007
MegaCore Version 7.2
2–7
8B10B Encoder/Decoder MegaCore Function User Guide
ALTERA [ ALTERA CORPORATION ]
