Simulate the Design
You can simulate your design using the generated VHDL and Verilog
HDL IP functional simulation models.
Simulate the
Design
f
For more information on IP functional simulation models, refer to the
Simulating Altera IP in Third-Party Simulation Tools chapter in Volume 3 of
the Quartus II Handbook.
Altera also provides a Verilog HDL demonstration testbench, including
scripts to compile and run the demonstration testbench using a variety of
simulators and models. This testbench demonstrates the typical behavior
of an 8B10B MegaCore function, and how to instantiate a model in a
design. The demonstration testbench does not perform any error
checking.
f
For a complete list of models or libraries required to simulate the 8B10B
Encoder/Decoder MegaCore function, refer to the _run_modelsim.tcl
scripts provided with the demonstration testbench.
IP Functional Simulation Model
To use the demonstration testbench with IP functional simulation models
in the ModelSim® simulator, follow these steps:
1. Start the ModelSim simulator.
2. From the ModelSim File menu, use Change Directory to change the
working directory to the directory where you created your 8B10B
Encoder/Decoder variation.
3. In the ModelSim Transcript window, execute the command
do<variation_name>_run_modelsim.tclwhich sets up the
required libraries, compiles the netlist files, and runs the testbench.
The ModelSim Transcript window displays messages from the
testbench reflecting the results of the simulation.
1
In all cases, the testbench is in Verilog HDL, therefore a license
to run mixed language simulations is required to run the
testbench with the VHDL model.
1
Altera recommends that you disable the auto-ROM replacement
feature in the Quartus II software. Enabling this feature
produces a smaller but slower MegaCore function.
2–12
MegaCore Version 7.2
Altera Corporation
October 2007
8B10B Encoder/Decoder MegaCore Function User Guide
ALTERA [ ALTERA CORPORATION ]
