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5CSEA2 参数 Datasheet PDF下载

5CSEA2图片预览
型号: 5CSEA2
PDF下载: 下载PDF文件 查看货源
内容描述: 旋风V器件手册 [Cyclone V Device Handbook]
分类和应用:
文件页数/大小: 74 页 / 1776 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–18  
Chapter 2: Device Datasheet for Cyclone V Devices  
Switching Characteristics  
Core Performance Specifications  
This section describes the clock tree, phase-locked loop (PLL), digital signal  
processing (DSP), and memory block specifications.  
Clock Tree Specifications  
Table 2–22 lists the clock tree specifications for Cyclone V devices.  
Table 2–22. Clock Tree Performance for Cyclone V Devices—Preliminary  
Performance  
Unit  
C6  
C7, I7  
Speed Grade  
C8, A7  
Speed Grade  
Symbol  
Speed Grade  
Global clock and Regional clock  
Peripheral clock  
550  
155  
550  
460  
155  
MHz  
MHz  
155  
PLL Specifications  
Table 2–23 lists the Cyclone V PLL specifications when operating in the commercial  
(0° to 85°C), industrial (–40° to 100°C), and automotive (–40° to 125°C) junction  
temperature ranges.  
Table 2–23. PLL Specifications for Cyclone V Devices—Preliminary (1) (Part 1 of 3)  
Symbol  
Parameter  
Min  
5
Typ  
50  
Max  
670 (2)  
622 (2)  
500 (2)  
325  
TBD (1)  
1600  
1400  
1300  
60  
550 (3)  
550 (3)  
460 (3)  
667 (3)  
667 (3)  
533 (3)  
55  
Unit  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
%
C6 speed grade  
fIN  
Input clock frequency  
C7, I7 speed grades  
C8, A7 speed grades  
5
5
fINPFD  
Integer input clock frequency to the PFD  
Fractional input clock frequency to the PFD  
5
fFINPFD  
50  
600  
600  
600  
40  
45  
C6 speed grade  
fVCO  
PLL VCO operating range  
C7, I7 speed grades  
C8, A7 speed grades  
tEINDUTY  
Input clock or external feedback clock input duty cycle  
C6 speed grade  
Output frequency for internal global  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
%
fOUT  
C7, I7 speed grades  
or regional clock  
C8, A7 speed grades  
C6 speed grade  
Output frequency for external clock  
C7, I7 speed grades  
output  
fOUT_EXT  
C8, A7 speed grades  
Duty cycle for external clock output (when set to 50%)  
External feedback clock compensation time  
Time required to reconfigure phase shift  
tOUTDUTY  
tFCOMP  
10  
TBD (1)  
ns  
tCONFIGPHASE  
tDYCONFIGCLK  
Dynamic configuration clock  
100  
MHz  
Time required to lock from end-of-device configuration or  
deassertion of areset  
tLOCK  
1
ms  
Cyclone V Device Handbook  
February 2012 Altera Corporation  
Volume 1: Device Overview and Datasheet  
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