Chapter 2: Device Datasheet for Cyclone V Devices
2–17
Switching Characteristics
Table 2–21 lists the Cyclone V GX transceiver block jitter specifications.
Table 2–21. Transceiver Block Jitter Specifications for Cyclone V GX Devices—Preliminary
C6
C7, I7
C8, A7
Symbol/
Description
Speed Grade
Speed Grade
Speed Grade
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
(1)
PCIe Transmit Jitter Generation
Total jitter at
2.5 Gbps (Gen1)
Compliance pattern
—
—
0.25
—
—
0.25
—
—
0.25
UI
UI
(1)
PCIe Receiver Jitter Tolerance
Total jitter at
2.5 Gbps (Gen1)
Compliance pattern
> 0.6
> 0.6
> 0.6
(2)
GIGE Transmit Jitter Generation
Deterministic jitter
(peak-to-peak)
Pattern = CRPAT
—
—
—
—
0.14
—
—
—
0.14
—
—
—
—
0.14
UI
UI
Total jitter
(peak-to-peak)
Pattern = CRPAT
0.279
—
0.279
0.279
(2)
GIGE Receiver Jitter Tolerance
Deterministic jitter
tolerance
(peak-to-peak)
Pattern = CJPAT
> 0.4
> 0.4
> 0.4
UI
UI
Combined
deterministic and
random jitter
tolerance
Pattern = CJPAT
> 0.66
> 0.66
> 0.66
(peak-to-peak)
Notes to Table 2–21:
(1) The jitter numbers for PIPE are compliant to the PCIe Base Specification 2.0.
(2) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
February 2012 Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
