2–14
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
Switching Characteristics
This section provides performance characteristics of Cyclone V core and periphery
blocks for commercial grade devices.
These characteristics can be designated as preliminary or final.
■
■
Preliminary characteristics are obtained using simulation results, process data,
and other known parameters. The title of these tables show the designation as
“Preliminary.”
Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 2–20 lists the Cyclone V GX transceiver specifications.
Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 1 of 3)
C6
C7, I7
C8, A7
Symbol/
Description
Speed Grade
Speed Grade
Speed Grade
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (1), HCSL, and LVDS
Input frequency from
REFCLKinput pins
—
—
—
27
45
—
—
—
550
55
27
45
—
—
—
550
55
27
45
—
—
—
550
55
MHz
%
Duty cycle
Peak-to-peak
differential input voltage
200
2000
200
2000
200
2000
mV
Spread-spectrum
modulating clock
frequency
PCIe
PCIe
30
—
33
30
—
33
30
—
33
kHz
—
0 to
0 to
0 to
Spread-spectrum
downspread
—
—
—
—
—
—
—
—
—
—
—
—
–0.5%
–0.5%
–0.5%
On-chip termination
resistors
—
—
100
100
100
Ω
(2)
(2)
VICM (AC coupled)
1.1
1.1 (2)
1.1
V
HCSL I/O
standard for the
PCIe reference
clock
VICM (DC coupled)
RREF
250
—
—
550
—
250
—
—
550
—
250
—
—
550
—
mV
2000
1%
2000
1%
2000
1%
—
Ω
Cyclone V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
