Chapter 1: Overview for Cyclone V Device Family
1–19
SoC FPGA with HPS
HPS–FPGA AXI Bridges
The HPS–FPGA bridges, which support the Advanced Microcontroller Bus
Architecture (AMBA®) Advanced eXtensible Interface (AXI™) specifications, consist
of the following bridges:
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FPGA-to-HPS AXI bridge—a high-performance bus supporting 32-, 64-, and
128-bit data widths that allows the FPGA fabric to master transactions to the slaves
in the HPS
HPS-to-FPGA AXI bridge—a high-performance bus supporting 32-, 64-, and
128-bit data widths that allows the HPS to master transactions to the slaves in the
FPGA fabric.
Lightweight HPS-to-FPGA AXI bridge—a lower performance 32-bit width bus
that allows the HPS to master transactions to the slaves in the FPGA fabric.
The HPS–FPGA AXI bridges also allow the FPGA fabric to access the memory shared
by one or both microprocessors, and provide asynchronous clock crossing with the
clock from the FPGA fabric.
HPS SDRAM Controller Subsystem
The HPS SDRAM controller subsystem contains a multiport SDRAM memory
controller and DDR PHY that are shared between the FPGA fabric (through the
FPGA-to-HPS SDRAM interface), the level 2 (L2) cache, and the level 3 (L3) system
interconnect. The FPGA-to-HPS SDRAM interface supports AMBA AXI and Avalon®
Memory-Mapped (Avalon-MM) interface standards, and provides up to four ports
with separate read and write directions.
To maximize memory performance, the SDRAM controller subsystem supports
command and data reordering, deficit round-robin arbitration with aging, and
high-priority bypass features. The SDRAM controller subsytem supports DDR2,
DDR3, LPDDR, or LPDDR2 devices up to 4 Gb in density and runs up to 400 MHz
(800 Mbps data rate).
For easy migration, the FPGA-to-HPS SDRAM interface is compatible with the
interface of the soft SDRAM memory controller IPs and hard SDRAM memory
controllers in the FPGA fabric.
FPGA Configuration and Processor Booting
The FPGA fabric and HPS in the SoC FPGA are powered independently. You can
reduce the clock frequencies or gate the clocks to reduce dynamic power, or shut
down the entire FPGA fabric to reduce total system power.
You can configure the FPGA fabric and boot the HPS independently, in any order,
providing you with more design flexibility:
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You can boot the HPS before you power up and configure the FPGA fabric. After
the system is running, the HPS reconfigures the FPGA fabric at any time under
program control or through the FPGA configuration controller.
You can power up both the HPS and the FPGA fabric together, configure the FPGA
fabric first, and then upload the boot code to the HPS from the FPGA fabric.
February 2012 Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
