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5CSEA2 参数 Datasheet PDF下载

5CSEA2图片预览
型号: 5CSEA2
PDF下载: 下载PDF文件 查看货源
内容描述: 旋风V器件手册 [Cyclone V Device Handbook]
分类和应用:
文件页数/大小: 74 页 / 1776 K
品牌: ALTERA [ ALTERA CORPORATION ]
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1–16  
Chapter 1: Overview for Cyclone V Device Family  
Enhanced Configuration and Configuration via Protocol  
Cyclone V devices have up to eight PLLs, each with nine output counters that you can  
use to reduce PLL usage in two ways:  
Reduce the number of oscillators that are required on your board by using  
fractional PLLs.  
Reduce the number of clock pins that are used in the device by synthesizing  
multiple clock frequencies from a single reference clock source.  
Cyclone V devices use a fractional PLL architecture in addition to the historical  
integer PLL. If you use the fractional PLL mode, you can use the PLLs for precision  
fractional-N frequency synthesis—removing the need for off-chip reference clock  
sources in your design. The transceiver fractional PLLs that are not used by the  
transceiver I/Os can be used as general purpose fractional PLLs by the FPGA fabric.  
Apart from frequency synthesis, on-chip clock deskew, jitter attenuation, counter  
reconfiguration, programmable output clock duty cycles, PLL cascading, and  
reference clock switchover, the PLLs in the Cyclone V devices also support the  
following key features:  
Programmable bandwidth  
User-mode reconfiguration of PLLs  
Low power mode for each fractional PLL  
Reference clock switchover  
Dynamic phase shift  
Direct, source synchronous, ZDB, external feedback, and LVDS compensation  
Enhanced Configuration and Configuration via Protocol  
Cyclone V devices support 3.3-V programming voltage and several configuration  
modes. Table 1–14 lists the configuration modes and features supported by the  
Cyclone V devices.  
Table 1–14. Configuration Modes and Features for Cyclone V Devices  
Maximum  
Data  
Width  
(Bit)  
Maximum  
Remote  
System  
Update  
Clock  
Rate  
Design  
Security  
Partial  
Reconfiguration  
Mode  
DataRate Decompression  
(Mbps)  
(MHz)  
AS through the EPCS  
and EPCQ serial  
configuration device  
x1, x4  
80  
v
v
v
PS through CPLD or  
external microcontroller  
x1  
125  
125  
125  
v
v
v
v
16-bit only  
v
Parallel  
flash loader  
FPP  
x8, x16  
x1, x2,  
x4 (1)  
CvP (PCIe)  
33  
33  
v
v
JTAG  
x1  
Note to Table 1–14:  
(1) The number of lanes instead of bit.  
Cyclone V Device Handbook  
February 2012 Altera Corporation  
Volume 1: Device Overview and Datasheet  
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