Chapter 1: Overview for Cyclone V Device Family
1–23
Document Revision History
Document Revision History
Table 1–15 lists the revision history for this document.
Table 1–15. Document Revision History
Date
Version
Changes
■ Updated Table 1–2, Table 1–3, and Table 1–6.
■ Updated “Cyclone V Family Plan” on page 1–4 and “Clock Networks and PLL Clock
February 2012
1.2
Sources” on page 1–15.
■ Updated Figure 1–1 and Figure 1–6.
■ Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and Table 1–6.
■ Updated Figure 1–4, Figure 1–5, Figure 1–6, Figure 1–7, and Figure 1–8.
■ Updated “System Peripherals” on page 1–18, “HPS–FPGA AXI Bridges” on page 1–19,
“HPS SDRAM Controller Subsystem” on page 1–19, “FPGA Configuration and Processor
Booting” on page 1–19, and “Hardware and Software Development” on page 1–20.
November 2011
October 2011
1.1
1.0
■ Minor text edits.
Initial release.
February 2012 Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet