Cyclone V Device Overview
CV-51001 | 2018.05.07
Maximum Resources
Table 10.
Maximum Resource Counts for Cyclone V SE Devices
Resource
Member Code
A5
A2
25
A4
40
A6
Logic Elements (LE) (K)
ALM
85
110
9,430
37,736
1,400
138
36
15,880
60,376
2,700
231
84
32,070
41,910
Register
128,300
166,036
Memory (Kb)
M10K
MLAB
3,970
5,570
480
621
Variable-precision DSP Block
18 x 18 Multiplier
FPGA PLL
87
112
72
168
5
174
224
5
6
6
HPS PLL
3
3
3
3
FPGA GPIO
145
181
32
145
181
32
288
288
HPS I/O
181
181
LVDS
Transmitter
Receiver
72
72
37
37
72
72
FPGA Hard Memory Controller
HPS Hard Memory Controller
Arm Cortex-A9 MPCore Processor
1
1
1
1
1
1
1
1
Single- or dual-
core
Single- or dual-
core
Single- or dual-core
Single- or dual-core
Related Information
True LVDS Buffers in Devices, I/O Features in Cyclone V Devices
Provides the number of LVDS channels in each device package.
Package Plan
Table 11.
Package Plan for Cyclone V SE Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific
I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
Member Code
U484
U672
F896
(19 mm)
(23 mm)
(31 mm)
FPGA GPIO
HPS I/O
151
FPGA GPIO
HPS I/O
181
FPGA GPIO
HPS I/O
—
A2
A4
A5
A6
66
66
66
66
145
145
145
145
—
—
151
181
—
151
181
288
288
181
151
181
181
Cyclone V Device Overview
13
ALTERA [ ALTERA CORPORATION ]
