AV-51002
2017.02.10
1-93
Glossary
Term
Definition
tFALL
Signal high-to-low transition time (80–20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input
Period jitter on the GPIO driven by a PLL
tOUTPJ_IO
tOUTPJ_DC
tRISE
Period jitter on the dedicated clock output driven by a PLL
Signal low-to-high transition time (20–80%)
Timing Unit Interval (TUI)
e timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/
(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
VCM(DC)
VICM
DC common mode input voltage.
Input common mode voltage—e common mode of the differential signal at the receiver.
VID
Input differential voltage sꢂing—e difference in voltage between the positive and complementary
conductors of a differential transmission at the receiver.
VDIF(AC)
VDIF(DC)
VIH
AC differential input voltage—Minimum AC input differential voltage required for switching.
DC differential input voltage— Minimum DC input differential voltage required for switching.
Voltage input high—e minimum positive voltage applied to the input which is accepted by the device as
a logic high.
VIH(AC)
VIH(DC)
VIL
High-level AC input voltage
High-level DC input voltage
Voltage input loꢂ—e maximum positive voltage applied to the input which is accepted by the device as
a logic low.
VIL(AC)
VIL(DC)
VOCM
VOD
Low-level AC input voltage
Low-level DC input voltage
Output common mode voltage—e common mode of the differential signal at the transmitter.
Output differential voltage sꢂing—e difference in voltage between the positive and complementary
conductors of a differential transmission line at the transmitter.
VSWING
VX
Differential input voltage
Input differential cross point voltage
Arria V GX, GT, SX, and ST Device Datasheet
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