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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
1-95  
Document Revision History  
Date  
Version  
Changes  
December 2015  
2015.12.16  
• Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria V Devices table.  
• Updated Fclk, Tdutycycle, and Tdssfrst specifications.  
• Added Tqspi_clk, Tdin_start, and Tdin_end specifications.  
• Removed Tdinmax specifications.  
• Updated the minimum specification for Tclk to 16.67 ns and removed the maximum specification in SPI  
Master Timing Requirements for Arria V Devices table.  
• Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria V Devices table.  
• Updated T clk to Tsdmmc_clk_out symbol.  
• Updated Tsdmmc_clk_out and Td specifications.  
• Added Tsdmmc_clk, Tsu, and Th specifications.  
• Removed Tdinmax specifications.  
• Updated the following diagrams:  
• Quad SPI Flash Timing Diagram  
• SD/MMC Timing Diagram  
• Updated configuration .rbf sizes for Arria V devices.  
• Changed instances of Quartus II to Quartus Prime.  
Arria V GX, GT, SX, and ST Device Datasheet  
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Altera Corporation  
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