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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
1-94  
Document Revision History  
Term  
Definition  
VOX  
W
Output differential cross point voltage  
High-speed I/O block—Clock boost factor  
Document Revision History  
Date  
Version  
Changes  
December 2016  
2016.12.09  
• Updated VICM (AC coupled) specifications in Receiver Specifications for Arria V GX and SX Devices table.  
• Added maximum specification for Td in Management Data Input/Output (MDIO) Timing Requirements for  
Arria V Devices table.  
• Updated Tinit specifications in the following tables:  
• FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices  
• FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices  
• AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V Devices  
• PS Timing Parameters for Arria V Devices  
June 2016  
2016.06.10  
• Changed pin capacitance to maximum values.  
• Updated SPI Master Timing Requirements for Arria V Devices table.  
• Added Tsu and Th specifications.  
• Removed Tdinmax specifications.  
• Updated SPI Master Timing Diagram.  
• Updated Tclk spec from maximum to minimum in I2C Timing Requirements for Arria V Devices table.  
Arria V GX, GT, SX, and ST Device Datasheet  
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Altera Corporation  
 
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