AV-51002
2017.02.10
2-64
FPP Configuration Timing when DCLK to DATA[] > 1
Symbol
Parameter
Minimum
Maximum
Unit
tCD2CU
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLK
—
—
period
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
tCD2CU
+
—
—
(8576 × CLKUSR
period) (215)
Related Information
•
DCLK-to-DATA[] Ratio (r) for FPP Configuration on page 2-57
• Configuration, Design Security, and Remote System Upgrades in Arria V Devices
(215)
To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
“Initialization” section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
Arria V GZ Device Datasheet
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