AV-51002
2017.02.10
2-66
Active Serial Configuration Timing
Symbol
Parameter
Minimum
Maximum
Unit
ns
tCO
DCLKfalling edge to AS_DATA0/ASDO output
Data setup time before falling edge on DCLK
Data hold time afer falling edge on DCLK
CONF_DONEhigh to user mode (216)
—
1.5
0
4
—
tSU
ns
tH
—
ns
tCD2UM
tCD2CU
175
437
—
μs
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLK
—
period
tCD2UMC CONF_DONEhigh to user mode with CLKUSRoption on
tCD2CU + (8576 × CLKUSR
—
—
period)
Table 2-59: DCLK Frequency Specification in the AS Configuration Scheme
is applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source.
e AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.
Minimum
5.3
Typical
7.9
Maximum
12.5
Unit
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
21.3
50.0
42.6
100.0
Related Information
•
Passive Serial Configuration Timing on page 2-67
• Configuration, Design Security, and Remote System Upgrades in Arria V Devices
(216)
To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on this pin, refer to the
“Initialization” section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
Arria V GZ Device Datasheet
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