Chapter 2: Device Datasheet for Arria V Devices
2–31
Switching Characteristics
Periphery Performance
This section describes periphery performance and the high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. GPIO
standards such as 3.3-, 2.5-, 1.8-, and 1.5-V LVTTL/LVCMOS are capable of a typical
167 MHz and 1.2 LVCMOS at 100 MHz interfacing frequency with a 10 pF load.
1
Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 2–29 lists high-speed I/O timing for Arria V devices.
Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary (1), (2), (3) (Part 1 of 3)
–4 Speed Grade
Min Typ Max
–5 Speed Grade
Min Typ Max
–6 Speed Grade
Min Typ Max
Symbol
Conditions
Unit
fHSCLK_in(input
clock
frequency)
True
Differential
I/O Standards
(5)
(5)
(5)
Clock boost factor W = 1 to 40
5
5
—
—
625
625
TBD
5
5
—
—
625
625
TBD
5
5
—
—
TBD
TBD
TBD
MHz
fHSCLK_in(input
clock
frequency)
Single Ended
Clock boost factor W = 1 to 40
MHz
I/O Standards
(4)
fHSCLK_in(input
clock
frequency)
Single Ended
Clock boost factor W = 1 to 40
5
5
—
—
5
5
—
—
5
5
—
—
MHz
MHz
I/O Standards
(3)
fHSCLK_OUT
(output clock
frequency)
(6)
(6)
(6)
—
625
625
TBD
February 2012 Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
