Chapter 2: Device Datasheet for Arria V Devices
2–27
Switching Characteristics
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks and temperature sensing diode specifications.
Clock Tree Specifications
Table 2–24 lists the clock tree specifications for Arria V devices.
Table 2–24. Clock Tree Performance for Arria V Devices—Preliminary
Performance
–C4 Speed Grade
Unit
Symbol
–C5, I5 Speed Grade
–C6 Speed Grade
Global clock and Regional clock
Peripheral clock
625
450
625
400
525
350
MHz
MHz
PLL Specifications
Table 2–25 lists the Arria V PLL specifications when operating in both the commercial
junction temperature range (0° to 85°C) and the industrial junction temperature range
(–40° to 100°C).
(1)
Table 2–25. PLL Specifications for Arria V Devices—Preliminary
(Part 1 of 3)
Min
Symbol
Parameter
Typ
—
—
—
—
—
—
—
—
—
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
(2)
Input clock frequency (–4 speed grade)
Input clock frequency (–5 speed grade)
Input clock frequency (–6 speed grade)
Integer input clock frequency to the PFD
Fractional input clock frequency to the PFD
PLL VCO operating range (–4 speed grade)
PLL VCO operating range (–5 speed grade)
PLL VCO operating range (–6 speed grade)
Input clock or external feedback clock input duty cycle
5
5
670
622
500
(2)
(2)
fIN
5
fINPFD
5
325
fFINPFD
50
600
600
600
40
TBD (1)
1600
1400
1300
60
fVCO
tEINDUTY
Output frequency for internal global or regional clock
(–4 speed grade)
(3)
—
—
—
—
—
—
500
MHz
MHz
MHz
Output frequency for internal global or regional clock
(–5 speed grade)
(3)
fOUT
500
Output frequency for internal global or regional clock
(–6 speed grade)
(3)
400
(3)
Output frequency for external clock output (–4 speed grade)
Output frequency for external clock output (–5 speed grade)
Output frequency for external clock output (–6 speed grade)
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
—
—
—
45
—
—
—
—
—
—
50
—
—
—
670
MHz
MHz
MHz
%
(3)
fOUT_EXT
622
(3)
500
tOUTDUTY
55
10
tFCOMP
ns
tCONFIGPHASE
tDYCONFIGCLK
Time required to reconfigure phase shift
TBD (1)
—
Dynamic Configuration Clock
100
MHz
February 2012 Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
