Chapter 2: Device Datasheet for Arria V Devices
2–35
Switching Characteristics
Figure 2–3 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
a data rate less than 1.25 Gbps.
Figure 2–3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
20 MHz
baud/1667
DQS Logic Block and Memory Output Clock Jitter Specifications
Table 2–32 lists the DQS phase shift error for Arria V devices.
Table 2–32. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria V
Devices—Preliminary (1), (2)
Number of DQS Delay
Buffer
–C4
Speed Grade
–C5, I5
Speed Grade
–C6
Speed Grade
Unit
2
57
58
74
ps
Notes to Table 2–32:
(1) The numbers are preliminary pending silicon characterization.
(2) This error specification is the absolute maximum and minimum error. For example, skew on two DQS delay buffers
in a –4 speed grade is 58 ps or 29 ps.
Table 2–33 lists the memory output clock jitter specifications for Arria V devices.
(1)
Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary
(Part 1 of 2)
–6
–4
–5
Clock
Speed Grade
Speed Grade
Speed Grade
Parameter
Symbol
Unit
Network
Min
–50
Max
50
Min
–55
Max
55
Min
–55
Max
55
Clock period jitter
Regional
Regional
Regional
Global
tJIT(per)
tJIT(cc)
ps
ps
ps
ps
ps
Cycle-to-cycle period jitter
Duty cycle jitter
–100
–50
100
50
–110
–82.5
–82.5
–165
110
82.5
82.5
165
–110
–82.5
–82.5
–165
110
82.5
82.5
165
tJIT(duty)
tJIT(per)
tJIT(cc)
Clock period jitter
–75
75
Cycle-to-cycle period jitter
Global
–150
150
February 2012 Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
