2–34
Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Table 2–30 lists the DPA lock time specifications for Arria V devices.
(1), (2), (3)
Table 2–30. DPA Lock Time Specifications for Arria V Devices—Preliminary
Number of Data
Number of
Transitions in One
Standard
Training Pattern
Repetitions per 256
Maximum
Repetition of the
Training Pattern
(4)
Data Transitions
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
Parallel Rapid I/O
10010000
10101010
32
Miscellaneous
01010101
32
Notes to Table 2–30:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in this table applies to both commercial and industrial grades.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 2–2 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
a data rate equal to 1.25 Gbps.
Figure 2–2. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to 1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
25
8.5
0.35
0.1
F3
F2
F1
F4
Jitter Frequency (Hz)
Table 2–31 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate equal to 1.25 Gbps.
Table 2–31. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.25 Gbps—Preliminary
Jitter Frequency (Hz)
Sinusoidal Jitter (UI)
25.000
F1
F2
F3
F4
10,000
17,565
25.000
1,493,000
50,000,000
0.350
0.350
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
