Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
Parameter
Maximum
Unit
pF
CVREFB
CCLKB
Input capacitance on bottom dual purpose VREF pin when used as VREF or user I/O pin
Input capacitance on bottom dual purpose clock input pins (12)
50
7
pF
CCLKLRT
Input capacitance on left/right/top dual purpose clock input pins (12)
6
pF
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
Table 17.
Internal Weak Pull-Up Resistor for Intel MAX 10 Devices
Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
Symbol
R_PU
Parameter
Condition
VCCIO = 3.3 V ± 5%
VCCIO = 3.0 V ± 5%
VCCIO = 2.5 V ± 5%
VCCIO = 1.8 V ± 5%
VCCIO = 1.5 V ± 5%
VCCIO = 1.2 V ± 5%
Min
7
Typ
12
13
15
25
36
82
Max
34
Unit
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
Value of I/O pin (dedicated and dual-purpose)
pull-up resistor before and during configuration,
as well as user mode if the programmable pull-up
resistor option is enabled
8
37
10
16
20
33
46
75
106
179
Hot-Socketing Specifications
Table 18.
Hot-Socketing Specifications for Intel MAX 10 Devices
Symbol
Parameter
Maximum
IIOPIN(DC)
IIOPIN(AC)
DC current per I/O pin
AC current per I/O pin
300 µA
(13)
8 mA
(11)
When VREF pin is used as regular input or output, Fmax performance is reduced due to higher pin capacitance. Using the VREF pin
capacitance specification from device datasheet, perform SI analysis on your board setup to determine the Fmax of your system.
(12)
10M40 and 10M50 devices have dual purpose clock input pins at top/bottom I/O banks.
Intel® MAX® 10 FPGA Device Datasheet
15
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