AS4C256M16D3
Figure 52. WRITE(BC4) to WRITE(BC8) OTF
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK
Notes 3
WRITE
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tCCD
tWR
4 Clocks
tWTR
Notes 4
Bank
Col n
Bank
Col b
ADDRESS
tWPRE
tWPST
tWPST
tWPRE
DQS, DQS#
Notes 2
Din
n
Din
n+1
Din
n+2
Din
n+3
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
DQ
WL = 5
WL = 5
NOTES:
1. WL = 5 (CWL = 5, AL = 0)
2. DIN n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during WRITE command at T4.
TRANSITIONING DATA
Don't Care
Figure 53. Refresh Command Timing
CK#
T0
T1
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tc0
Tc1
Tc2
Tc3
CK
REF
NOP
NOP
REF
NOP
NOP
VALID
VALID
VALID
VALID
VALID
REF
VALID
VALID
VALID
COMMAND
tRFC (min)
tRFC
tREFI (max. 9 * tREFI)
DRAM must be idle
DRAM must be idle
NOTES:
1. Only NOP/DES commands allowed after Refresh command registered until tRFC(min) expires.
2. Time interval between two Refresh commands may be extended to a maximum of 9 x tREFI.
TIME BREAK
TRANSITIONING DATA
Don't Care
Figure 54. Self-Refresh Entry/Exit Timing
T0
T1
T2
Ta0
Tb0
Tc0
tCKSRX
Tc1
Td0
Teo
Tf0
CK#
CK
tCKSRE
tIS tCPDED
VALID
VALID
VALID
CKE
ODT
tCKESR
tIS
ODTL
Notes 1
NOP
Notes 2
Notes 3
VALID
SRX
COMMAND
ADDR
NOP
SRE
NOP
VALID
tXS
VALID
VALID
tRP
tXSDLL
Exit Self
Refresh
Enter Self
Refresh
NOTES:
1. Only NOP or DES command.
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
TIME BREAK
Don't Care
Confidential
71
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
