AS4C256M16D3
Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down
definition, these modes are:
- Any bank active with CKE high
- Refresh with CKE high
- Idle mode with CKE high
- Active power down mode (regardless of MR0 bit A12)
- Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled
by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0}
via a mode register set command during DLL-off mode.
In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising
clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT
latency is tied to the write latency (WL) by: ODTLon = WL - 2; ODTLoff = WL-2.
ODT Latency and Posted ODT
In synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to
the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive
Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details,
refer to DDR3 SDRAM latency definitions.
Table 25. ODT Latency
Symbol
Parameter
DDR3-1600
Unit
ODT turn on
Latency
ODT turn off
Latency
ODTLon
ODTLoff
WL – 2 = CWL + AL -2
WL – 2 = CWL + AL -2
tCK
tCK
Timing Parameters
In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF
min/max.
Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT
resistance begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT
resistance is fully on. Both are measured from ODTLon.
Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance.
Maximum RTT turn off time (tAOF max) is the point in time when the on-die termination has reached high
impedance. Both are measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the
SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write
command. ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the
registration of a write command until ODT is registered low.
ODT during Reads
As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock
cycle before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end
of the post-amble as shown in the following figure. DRAM turns on the termination when it stops driving which is
determined by tHZ. If DRAM stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops
driving late (i.e. tHZ is late), then DRAM complies with tAONmax timing. Note that ODT may be disabled earlier
before the Read and enabled later after the Read than shown in this example in Figure 11.
.
Confidential
49
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
