AS4C256M16D3
On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination
resistance. For x16 configuration, ODT is applied to each DQU, DQL, DQSU, DQSU#, DQSL, DQSL#, DMU and
DML signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory
channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM
devices. More details about ODT control modes and ODT timing modes can be found further down in this
document.
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown in Figure 10.
Figure 21. Functional representation of ODT
ODT
VDDQ / 2
RTT
To other circuitry
like RCV,...
Switch
DQ, DQS, DM
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control
information. The value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if
the Mode Register MR1 and MR2 are programmed to disable ODT and in self-refresh mode.
ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of
RTT is determined by the settings of those bits.
Application: Controller sends WR command together with ODT asserted.
One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR)
DRAM does not use any write or read command decode information.
Table 24. Termination Truth Table
ODT pin
DRAM Termination State
0
1
OFF
On, (Off, if disabled by MR1 (A2, A6, A9) and MR2 (A9, A10) in general)
Confidential
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Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
