2Gb DDR3L – AS4C128M16D3L
- Write Recovery
The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with tRP
to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by dividing tWR
(ns) by tCK (ns) and rounding up to the next integer: WR min [cycles] = Roundup (tWR [ns]/tCK [ns]). The WR
must be programmed to be equal or larger than tWR (min).
- Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or
‘slow-exit’, the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit
requires tXPDLL to be met prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is
maintained after entering precharge power-down and upon exiting power-down requires tXP to be met prior to
the next valid command.
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom
impedance, additive latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low
on CS#, RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states of address pins
according to the following figure.
Table 7. Extended Mode Register EMR (1) Bitmap
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8
A7 A6 A5
A4 A3
AL
A2
A1
A0 Address Field
0*1
0
1
Qoff
DLL Mode Register (1)
0*1
0*1 0*1
0*1
Rtt_Nom
Rtt_Nom
Rtt_Nom
Level
D.I.C
D.I.C
DLL Enable
Enable
BA1 BA0 MRS mode
A4 A3
Additive Latency
0 (AL disabled)
CL – 1
A0
0
0
0
1
0
1
0
MR0
MR1
MR2
0
0
1
0
1
0
Disable
1
CL – 2
1
1
MR3
1
1
Reserved
A12
Qoff *2
A9 A6 A2
Rtt_Nom *3
0
1
Output buffer enabled
Output buffer disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Rtt_Nom disabled
RZQ/4
Write leveling enable
Disabled
A7
0
RZQ/2
RZQ/6
1
Enabled
RZQ/12 *4
RZQ/8 *4
Reserved
Reserved
Note: RZQ = 240 Ω
Output Driver Impedance Control
A5
0
A1
0
RZQ/6
RZQ/7
Note: RZQ = 240 Ω
0
1
1
0
Reserved
Reserved
1
1
Note 1:
Note 2:
Note 3:
Reserved for future use and must be set to 0 when programming the MR.
Outputs disabled - DQs, DQSs, DQS#s.
In Write leveling Mode (MR1 [bit7] = 1) with MR1 [bit12] =1, all RTT_Nom settings are allowed; in Write
Leveling Mode (MR1 [bit7] = 1) with MR1 [bit12]=0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are
allowed.
Note 4:
If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
Confidential
16
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
