2Gb DDR3L – AS4C128M16D3L
Figure 7. tMOD timing
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
CK#
CK
NOP/DES
VALID
NOP/DES
VALID
NOP/DES
VALID
NOP/DES
VALID
NOP/DES
VALID
VALID
VALID
VALID
VALID
VALID
VALID
MRS
VALID
VALID
VALID
VALID
COMMAND
ADDRESS
VALID
CKE
Old Settings
Updating Settings
tMOD
New Settings
Settings
RTT_Nom ENABLED prior and/or after MRS command
ODTLoff + 1
VALID
VALID
VALID
VALID
ODT
ODT
RTT_Nom DISABLED prior and after MRS command
VALID VALID VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
TIME BREAK
Don't Care
The mode register contents can be changed using the same command and timing requirements during normal
operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data
bursts are completed and CKE is high prior to writing into the mode register. The mode registers are divided into
various fields depending on the functionality and/or modes.
Confidential
13
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
