2Gb DDR3L – AS4C128M16D3L
Register Definition
Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers,
provided by the DDR3L SDRAM, as user defined variables and they must be programmed via a Mode Register
Set (MRS) command. As the default values of the Mode Registers are not defined, contents of Mode Registers
must be fully initialized and/or re-initialized, i.e., written, after power up and/or reset for proper operation. Also the
contents of the Mode Registers can be altered by re-executing the MRS command during normal operation. When
programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address
fields within the accessed mode register must be redefined when the MRS command is issued. MRS command
and DLL Reset do not affect array contents, which mean these commands can be executed any time after power-
up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the mode
register and is the minimum time required between two MRS commands shown in Figure of tMRD timing.
Figure 6. tMRD timing
T0
T1
T2
Ta0
Ta1
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
CK#
CK
NOP/DES
VALID
NOP/DES
VALID
NOP/DES
VALID
NOP/DES
VALID
VALID
VALID
VALID
VALID
VALID
VALID
MRS
MRS
VALID
VALID
VALID
VALID
COMMAND
ADDRESS
VALID
VALID
CKE
Old Settings
Updating Settings
New Settings
Settings
tMRD
tMOD
RTT_Nom ENABLED prior and/or after MRS command
ODTLoff + 1
VALID
VALID
VALID
VALID
ODT
ODT
RTT_Nom DISABLED prior and after MRS command
VALID VALID VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
TIME BREAK
Don't Care
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except
DLL reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP
and DES shown in Figure of tMOD timing.
Confidential
12
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
