2Gb DDR3L – AS4C128M16D3L
- Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is
selected via bit A3 as shown in the MR0 Definition as above figure. The ordering of access within a burst is
determined by the burst length, burst type, and the starting column address. The burst length is defined by bits
A0-A1. Burst lengths options include fix BC4, fixed BL8, and on the fly which allow BC4 or BL8 to be selected
coincident with the registration of a Read or Write command via A12/BC#
Table 6. Burst Type and Burst Order
Starting Column
Read
Write
Sequential
A3=0
Interleave
A3=1
Address
Burst Length
Note
A2
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
V
A1
0
0
1
1
0
0
1
1
V
V
0
0
1
1
0
0
1
1
V
A0
0
1
0
1
0
1
0
1
V
V
0
1
0
1
0
1
0
1
V
0, 1, 2, 3, T, T, T, T 0, 1, 2, 3, T, T, T, T
1, 2, 3, 0, T, T, T, T 1, 0, 3, 2, T, T, T, T
2, 3, 0, 1, T, T, T, T 2, 3, 0, 1, T, T, T, T
3, 0, 1, 2, T, T, T, T 3, 2, 1, 0, T, T, T, T
4, 5, 6, 7, T, T, T, T 4, 5, 6, 7, T, T, T, T
5, 6, 7, 4, T, T, T, T 5, 4, 7, 6, T, T, T, T
6, 7, 4, 5, T, T, T, T 6, 7, 4, 5, T, T, T, T
7, 4, 5, 6, T, T, T, T 7, 6, 5, 4, T, T, T, T
0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X 4, 5, 6, 7, X, X, X, X
Read
Write
1, 2, 3
4
Chop
1, 2, 4, 5
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
Read
Write
2
8
2, 4
Note 1: In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier
than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case
of burst length being selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like
a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be
pulled in by two clocks.
Note 2: 0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
Note 3: T: Output driver for data and strobes are in high impedance.
Note 4: V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
Note 5: X: Don’t Care.
- CAS Latency
The CAS Latency is defined by MR0 (bit A2, A4~A6) as shown in the MR0 Definition figure. CAS Latency is the
delay, in clock cycles, between the internal Read command and the availability of the first bit of output data.
DDR3L SDRAM does not support any half clock latencies. The overall Read Latency (RL) is defined as
Additive Latency (AL) + CAS Latency (CL); RL = AL + CL.
- Test Mode
The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in
the MR0 definition figure. Programming bit A7 to a ‘1’ places the DDR3L SDRAM into a test mode that is only
used by the DRAM manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.
- DLL Reset
The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has
been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset
function is used, tDLLK must be met before any functions that require the DLL can be used (i.e. Read
commands or ODT synchronous operations.)
Confidential
15
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
