ASAHI KASEI
[AK8817/18]
AK8817VQ/AK8818VQ
Pin#
Pin Name
I/O
Functional Outline
1
2
3
N.C.
N.C.
-
-
For normal operation, left open.
For normal operation, left open.
Analog power supply pin.
AVDD
P
IREF output pin. Connect this pin to Analog ground via a 12k ohm resistor
( better than +/- 1% accuracy ).
On-chip VREF output pin.
AVSS level is output on this pin at PDN = L.
Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.
4
5
IREF
O
O
VREF
6
7
UD4
UD3
UD2
UD1
UD0
N.C.
N.C.
N.C.
O
O
O
O
O
-
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
For normal operation, left open.
8
9
10
11
12
13
-
For normal operation, left open.
-
For normal operation, left open.
Internal clock is inverted (internal operation timing edge is inverted.)
Connect to either DVDD or DGND.
14
CLKINV
I
Clock input pin.
Input a clock which is synchronized with data.
When to input 601 data : 27 MHz.
15
CLKIN
I
When to input square pixel data : 24.5454 MHz ( NTSC )/ 29.50 MHz ( PAL )
16
17
DVSS
DVDD
G
P
Digital ground pin (digital core ground).
Digital power supply pin (digital core power supply).
Data Video Signal input pin (MSB).
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
18
19
20
21
22
D7
D6
D5
D4
D3
I
I
I
I
I
AK8817: Video Data Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
AK8818: N.C.
D2 (17)
N.C. (18)
23
I
For normal operation, left open.
24
25
N.C.
N.C.
-
-
For normal operation, left open.
For normal operation, left open.
AK8817: N.C.
N.C. (17)
D2 (18)
For normal operation, left open.
AK8818: Video Data Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
26
I
27
28
TEST
D1
I
I
For normal operation, connect to ground.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin (LSB).
Hi-Z input is acceptable to this pin at PDN = L.
29
30
D0
I
PVDD
P
Power supply pin for chip pad.
Rev.001E
7
2009 / 12
AKM [ ASAHI KASEI MICROSYSTEMS ]
