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AK8817VQ 参数 Datasheet PDF下载

AK8817VQ图片预览
型号: AK8817VQ
PDF下载: 下载PDF文件 查看货源
内容描述: NTSC / PAL数字视频编码器 [NTSC/PAL Digital Video Encoder]
分类和应用: 转换器色度信号转换器消费电路商用集成电路编码器
文件页数/大小: 50 页 / 427 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK8817/18]  
Pin Functional Description  
AK8817VG / AK8818VG  
AK8818 is different pin assignment from AK8817.  
Pin#  
Pin Name  
I/O  
Functional Outline  
Clock input pin.  
Input a clock which is synchronized with data.  
When to input 601 data : 27 MHz.  
When to input square pixel data : 24.5454 MHz ( NTSC )/ 29.50 MHz ( PAL )  
Internal clock is inverted (internal operation timing edge is inverted.)  
Connect to either PVDD or PVSS(DGND).  
Power Down Pin. After returning from PD mode to normal operation, RESET  
Sequence should be done to AK8817/18.  
G2  
F1  
B5  
CLKIN  
I
I
I
CLKINV  
PDN  
“L “(GND level): Power-down  
“H “: normal operation  
Reset input pin. In order to initialize the device , an initialization must be made in  
accordance with the reset sequence.  
“L “ : reset  
A6  
RSTN  
I
“H “ : normal operation  
Hi-Z input is acceptable to this pin at PDN = L.  
I2C data pin.  
This pin is pulled-up to PVDD.  
C7  
B6  
SDA  
SCL  
I
I
Hi-Z input is possible when PDN is at low.  
SDA input is not accepted during the reset sequence operation.  
I2C clock input pin  
An input level of lower-than-PVDD should be input.  
Hi-Z input is possible when PDN is at low.  
SCL input is not accepted during the reset sequence operation.  
Data Video Signal input pin (MSB).  
F4  
G4  
F5  
G4  
F5  
G5  
F6  
G6  
F7  
E6  
C6  
D7  
D7  
D6  
D5  
D5  
D6  
D4  
D3  
D2  
D1  
D0  
HDI  
VDI  
I
I
I
I
I
I
I
I
I
I
I
I
Hi-Z input is acceptable to this pin at PDN = L.  
Data Video Signal input pin. (AK8817)  
Hi-Z input is acceptable to this pin at PDN = L.  
Data Video Signal input pin. (AK8817)  
Hi-Z input is acceptable to this pin at PDN = L.  
Data Video Signal input pin. (AK8818)  
Hi-Z input is acceptable to this pin at PDN = L.  
Data Video Signal input pin. (AK8818)  
Hi-Z input is acceptable to this pin at PDN = L.  
Data Video Signal input pin.  
Hi-Z input is acceptable to this pin at PDN = L.  
Data Video Signal input pin.  
Hi-Z input is acceptable to this pin at PDN = L.  
Data Video Signal input pin.  
Hi-Z input is acceptable to this pin at PDN = L.  
Data Video Signal input pin.  
Hi-Z input is acceptable to this pin at PDN = L.  
Data Video Signal input pin (LSB).  
Hi-Z input is acceptable to this pin at PDN = L.  
Horizontal SYNC signal input pin.  
Hi-Z input is acceptable to this pin at PDN = L.  
Vertical SYNC signal input pin.  
Hi-Z input is acceptable to this pin at PDN = L.  
On-chip VREF output pin.  
C1  
VREF  
O
AVSS level is output on this pin at PDN = L.  
Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.  
IREF output pin. Connect this pin to Analog ground via a 12k ohm resistor  
( better than +/- 1% accuracy ).  
DAC output pin. Connect this pin to Analog ground via a 390 ohm resistor  
( better than +/- 1% accuracy ).  
C2  
A2  
IREF  
O
O
DACOUT  
A4  
A3  
B1  
B2  
A5, G3  
B4, F3  
VOUT  
SAG  
AVDD  
AVSS  
DVDD  
DVSS  
O
I/O  
P
G
P
Video output pin.  
SAG Compensation Input pin  
Analog power supply pin.  
Analog ground pin.  
Digital power supply pin (digital core power supply).  
Digital ground pin (digital core ground).  
G
Rev.001E  
5
2009 / 12