ASAHI KASEI
[AK8817/18]
E7
D6
PVDD
PVSS
P
G
Power supply pin for chip pad.
Ground pin for PVDD.
Substrate ground pin.
Connect this pin to Analog ground
B3
BVSS
G
G7
B7
TEST
ATPG
I
I
For normal operation, connect to ground.
For normal operation, connect to ground.
D2
D1
E2
E1
F2
UD4
UD3
UD2
UD1
UD0
O
O
O
I/O
I/O
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
Test I/O pin. For normal operation, left open.
Test I/O pin. For normal operation, left open.
C3
A1, A7,
G1
N.C.
N.C.
-
-
Index pin. For normal operation, left open.
For normal operation, left open.
Rev.001E
6
2009 / 12
AKM [ ASAHI KASEI MICROSYSTEMS ]
