[ASAHI KASEI]
[AK7740ET]
3. Block diagram
LRCLK
BITCLK CLKOUT XTI XTO SMODE
LRCLK BITCLK CLKOUT
XTI XTO SMODE
INIT_RESET
S_RESET
INIT_RESET
S_RESET
AINL-
OUTAE
CONTROLLER
SDOUTA
AINL-
ADC
SW3
AINL+
AINL1
AINL2
AINL3
AINL4
AINR-
SDINA
SDIN
AINL+
SW0
SDINA
SDIN
RQ
RQ
SI
SDATA
DSP
AINR-
AINR+
SI
SO
AINR+
AINR1
AINR2
AINR3
AINR4
VREFH
VCOM
SO
SCLK
RDY
SCLK
RDY
DRDY
ISEL[2:0]
SW2
VREF
DRDY
SDOUTD1
AOUTL
SDATA
AOUTL1
AOUTR1
DAC1
JX
JX
AOUTR
SW2
SW1
SDOUTD2
SDOUT
AOUTL2
AOUTR2
AOUTL
AOUTR
DAC2
SDATA
SDOUT
72kbit DLRAM
* SW1,SW2,SW3,ISEL[2:0],
OUTAE control register
Note)
C
A
B
When C is “L”(0) then A connects with Q.
Q
This block diagram is a simplified illustration of the AK7740; it is not a circuit diagram.
<Pre-E-01>
- 2 -
2006/10
AKM [ ASAHI KASEI MICROSYSTEMS ]
