ASAHI KASEI
[AK5351]
Digital Connections
To minimize digital originated noise, connect the ADC digital outputs only to CMOS inputs. Logic families of
4000B, 74HC, 74AC, 74ACT and 74HCT series are suitable.
Multiple AK5351
In systems where multiple ADC's are required, care must be taken to insure the internal clocks are
synchronized between converters to make simultaneous sampling. In slave mode, synchronous sampling is
achieved by supplying the same MCLK and LRCK to all converters. In master mode, the same PD signal is
supplied to each ADC. The PD state is released at the first rising edge of MCLK after bringing PD into high.
Hence, if the rising edge of PD and rising edge of MCLK coincides together the sampling difference among
the ADC's modulator would occur.The difference could be 1/256fs in the sampling clock(64fs) of the
modulator, typically 81ns at fs=48kHz.
0166-E-00
1997/4
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AKM [ ASAHI KASEI MICROSYSTEMS ]
